Recently, a synchronous memory which performs an operation synchronized with a clock signal, has come into widespread use as a main memory of, for example, a personal computer. In particular, in a clock-synchronous memory such as a DDR (Double Date Rate) memory, input/output data need to be correctly synchronized with respect to an external clock signal. Hence, a DLL (Delay Lock Loop) circuit that generates an internal clock signal, synchronized with the external clock signal, is indispensable.
The DLL circuit is provided with a phase detection circuit that detects whether or not the internal clock signal is correctly in phase with the external clock signal.
FIG. 5 shows a typical configuration of the phase detection circuit of this sort of the related technique. Referring to FIG. 5, the phase detection circuit includes
nMOS transistors M1 and M4 which have sources connected to a low potential power supply VSS1, gates supplied with an internal clock RCLK in common, and drains coupled together;
an inverter INV1 that receives the internal clock RCLK to output its inverted signal (delay time=td1);
nMOS transistors M2 and M5 which have sources connected to the coupled drains of the nMOS transistors M1 and M4, gates supplied with an output signal of the inverter INV1 in common, and drains coupled together;
nMOS transistors M3 and M6 which have sources connected to the coupled drains of the nMOS transistors M2 and M5, gates supplied with an external clock signal CK and a signal /CK that is reverse-phased respect to the clock signal CK, and drains connected to nodes LSAT and LSAB (termed sense nodes), respectively;
pMOS transistors MP11 and MP12 which have sources connected in common to a high potential power supply VDD1, gates connected in common to an equalization signal /EQ which is activated at a Low level, and drains connected to the sense nodes LSAT and LSAB;
a PMOS transistor MP13 which is connected between the drains of the pMOS transistors MP11 and MP12, and has a gate connected to the signal /EQ;
a differential amplifier (also termed a ‘sense amplifier’ or a ‘differential sense amplifier) AMP that has differential inputs connected to the sense nodes LSAT and LSAB, respectively; and
a latch circuit 11 that latches an output (single-ended output) of the sense amplifier AMP to produce the so latched sense amplifier output as a phase adjustment signal LOUT.
In the terms ‘sense node LSAT’ and ‘sense node LSAB’, T and A denote True and Bar, respectively. These sense nodes thus differentially transfer a signal. The internal clock signal has an amplitude between VDD1 and VSS1, while the external clock signals CK and /CK have an amplitude between VDD2 and VSS2. Normally, the amplitudes of the external clock signals CK and /CK are smaller than the amplitude of the internal clock signal. The center of amplitude of the external clock signals CK and /CK is set so as to be approximately equal to that of the internal clock signal RCLK, though not limited thereto. Since the amplitude of the external clock signals CK and /CK is smaller than that of the internal clock signal RCLK, as stated above, VDD1 is higher in potential than VDD2, while VSS1 is lower in potential than VSS2.
The operation of the phase detection circuit of FIG. 5 will now be described.
Before starting the phase detection operation, the equalization signal /EQ is set to Low level. This causes the pMOS transistors MP11 to MP13 to be made conductive, so that the sense nodes LSAT, LSAB are both precharged and equalized at a power supply potential VDD1 level.
The equalization signal /EQ is then set to High level to cancel precharging/equalization. If, in this state, the internal clock signal RCLK rises from the Low level (VSS1) to the High level (VDD1), the nMOS transistors M1 and M4 are made conductive.
An output signal of the inverter INV1 is at High level (VDD1) when the internal clock signal RCLK remains Low (VSS1). The output signal of the inverter INV1 falls from the High level (VDD1) to the Low level (VSS1) with a delay of td1 from a time point of rising of the internal clock signal RCLK from the Low level (VSS1) to the High level (VDD1).
The time interval from the rising of the internal clock signal RCLK until the fall of the output signal of the inverter INV1 corresponds to the delay time td1 of the inverter INV1. During this time interval, the internal clock signal RCLK and an output signal of the inverter INV1 (signal obtained on inverting RCLK and delaying it by td1) are both High (VDD1), so that the nMOS transistors M1, M2, M4, and M5 are made conductive. That is, the delay time td1 of the inverter INV1 prescribes the time interval during which the nMOS transistors M1, M2, M4 and M5 are conductive simultaneously, and hence the sampling interval by the phase detection circuit.
In FIG. 5, the sources of the nMOS transistors M2 and M5 which have gates supplied with the output signal of the inverter INV1 in common, are connected to the coupled drains of the nMOS transistors M1 and M4. Hence, the gate-to-source voltages of the nMOS transistors M2 and M5 are identical, and hence the nMOS transistors M2 and M5 are set in a conduction state or a non-conduction state in common.
The source potentials of the nMOS transistors M3 and M6 are common (the coupled sources of the nMOS transistors M3 and M6 are connected to the coupled drains of the nMOS transistors M2 and M5). The nMOS transistors M3 and M6 are made conductive when their gate-to-source voltages are not lower than a threshold voltage.
The amplitude of the external clock signals CK and /CK is smaller than that of the internal clock signal RCLK. Hence if the nMOS transistors M1 to M6 are fabricated to have a size corresponding to the amplitude of the internal clock signal RCLK, that is, the threshold voltages of the nMOS transistors M1 to M6 are set to have a value corresponding to the power supply voltages VDD1 and VSS1, the gate-to-source voltages of the nMOS transistors M3 and M6, whose gates receive the external clock signals CK and /CK, do not become smaller than the threshold value when the external clock signals CK and /CK assume Low level (VDD2). Hence, the nMOS transistors M3 and M6 receiving the external clock signals CK and /CK at gates thereof are both made conductive.
In this case, the current (drain current) that flows through one of the nMOS transistors M3 and M6 receiving one of the external clock signals CK and /CK having the High level (VDD2) at its gate becomes larger than the current (drain current) that flows through the other transistor receiving the Low level (VSS2) at its gate. The reason for this is that the gate-to-source voltage of the one of the nMOS transistors M3 and M6 receiving the High level (VDD2) of the external clock signal at its gate becomes larger than the gate-to-source voltage of the other transistor receiving the Low level (VSS2) of the external clock signal at its gate.
On the other hand, in case one of the nMOS transistors M3 and M6 receiving the external clock signal of the High level (VDD2) at gates thereof is in a conduction state, the other transistor, receiving the Low level external clock signal (VSS2), may be in a non-conduction state, depending on the size of the nMOS transistors M1 to M6, the amplitude and the common voltage of the external clock signals CK and /CK differentially transmitted.
In case the external clock signal CK rises to High (VDD2) from Low level (VSS2) before the internal clock signal RCLK rises from the Low level (VSS1) to the High level (VDD1), the external clock signal CK is at High level (VDD1) during the sampling period. This sampling period having a time width td1, begins as the transistors M1, M2, M4 and M5 change from a non-conduction state to a conduction state in response to the rise of the internal clock signal RCLK.
As a result, the nMOS transistor M3 is made conductive to render a discharge path between the sense node LSAT and the low-potential power supply VSS1 (LSAT→M3→M2→M1→VSS1) electrically conductive. On the other hand, since the reverse-phase external clock signal /CK is Low (VSS2), the nMOS transistor M6 is either in a conduction state in which the drain current of the nMOS transistor M6 is smaller than that of the nMOS transistor M3, or in a non-conduction state. A discharge path between the sense node LSAB and the low potential power supply VSS1 (LSAB→M6→M5→M4→VSS1) is either in a conduction state with the discharge current smaller than that on the LSAT side, or in a non-conduction state.
The discharging of the sense nodes LSAT and LSAB occurs, during the sampling period, in response to the High level (VDD2)/Low level (VSS2) of the external clock signals CK and /CK. It is observed that the sampling period begins with a time point of transition from the non-conduction states to the conduction states of the transistors M1, M2, M4 and M5 in response to the rise of the internal clock signal RCLK, and is prescribed as the delay time td1 of the inverter INV1.
For example, if the phase of the external clock signal CLK advances with respect to the internal clock signal RCLK, the level of the clock signal during the sampling period is set to High level (VDD1). Hence, at the end of the sampling period, the potentials on the sense nodes LSAT and LSAB are such that LSAT<LSAB.
The sense amplifier AMP has a non-inverting input terminal (−) and an inverting input terminal (+) connected to the sense nodes LSAT and LSAB, respectively, and amplifies the difference between the potentials of the sense nodes LSAT and LSAB. The amplified result is delivered, as a single-ended output of a High level (VDD1) or a Low level (VSS1), to a latch circuit L1. The latch circuit L1 outputs the signal supplied from the sense amplifier AMP, as a phase adjustment signal LOUT.
If the potential relationship between the sense nodes LSAT and LSAB is such that LSAT<LSAB, the output of the sense amplifier AMP is High (VDD1).
On the other hand, if the external clock signal CK rises from the Low level (VSS2) to the High level (VDD2) at a time delayed from the rise of the internal clock signal RCLK from the Low level (VSS1) to the High level (VDD1), the external clock signal CK is set to Low (VSS2) and the reverse-phased external clock signal /CK, is set to High (VDD2) during the sampling period that has a time duration td1 and starts at the time point of the rise of the internal clock signal RCLK.
As a result, the nMOS transistor M6 is made conductive, and hence the discharge path between the sense node LSAB and the low potential power supply VSS (LSAB→M6→M5→M4→VSS1) is rendered conductive. At this time, the external clock signal CK is at Low level (VSS2). Hence, the nMOS transistor M3 is either in a conduction state, with the drain current smaller than that of the nMOS transistor M6, or in a non-conduction state. The discharge current in the discharge path between the sense node LSAT and the low-potential power supply VSS1 (LSAT→M3→M2→M1→VSS1) is smaller than that on the LSAB side, or the discharge path is made non-conductive.
That is, when the external clock signal CK has a phase delayed with respect to the internal clock signal RCLK, the potential at the sense nodes LSAT and LSAB at the end of the sampling period is such that LSAB<LSAT. The output of the sense amplifier AMP goes to Low level (VSS1).
It is seen from above that the difference in the potential between the sense nodes LSAT and LSAB at the end of the sampling period represents the phase relationship between the internal clock signal RCLK and the external clock signal CK.
In the configuration example of FIG. 5, the sense amplifier AMP receives the internal clock signal RCLK as an activation control signal, and is activated during the period when the internal clock signal RCLK is High (VDD1). However, the sense amplifier AMP is as a matter of course not limited to such an arrangement.
As regards the phase detection circuit for detecting the phase difference of a plurality of signals, reference may be made to, for example, the Patent Document 1.
[Patent Document 1]
    JP Patent Kokai Publication No. JP2002-296326A